As opposed to planar complementary metal-oxide-semiconductor (CMOS) devices, vertical field effect transistors (VFET) devices are oriented with a vertical fin channel disposed on a bottom source/drain and a top source/drain disposed on the fin channel. VFET devices are being pursued as a viable CMOS architecture to continue CMOS scaling.
Unwanted variations such as fin pitch walking can be introduced during fabrication of VFET devices. Fin pitch walking is undesirable as it results in variation in fin height which in turn results in variation in bottom spacer height and thus gate length variation.
Therefore, techniques which improve gate length uniformity in VTFET devices would be desirable.